1. Field of the Invention
The present invention relates to a voltage level detector, and more particularly, to a back bias voltage level detector. Although the present invention is suitable for a wide scope of applications, it is particularly suitable for constantly maintaining a back bias voltage with respect to the variation of an external voltage and enhancing a junction reliability of an NMOS pull-down transistor.
2. Description of the Related Art
FIG. 1 is a block diagram illustrating a conventional back bias voltage generator.
As shown in FIG. 1, the conventional back bias voltage generator includes a back bias voltage level detector 1 for receiving a back bias voltage V.sub.BB and outputting an oscillation enable signal OSCEN, a back bias voltage oscillator 2 for receiving the oscillation enable signal OSCEN and outputting a pulse signal OSC having a constant period, and a back bias voltage pump 3 for receiving the pulse signal OSC and outputting the back bias voltage V.sub.BB.
The operation of the conventional back bias voltage generator will now be explained with reference to the accompanying drawings.
The back bias voltage level detector 1 outputs an oscillation enable signal OSCEN until the back bias voltage V.sub.BB becomes a predetermined level, and the back bias voltage oscillator 2 receives the oscillation enable signal OSCEN and outputs the pulse signal OSC having a predetermined period, and the back bias voltage pump 3 receives the pulse signal OSC from the back bias voltage oscillator 2 and pumps a negative electric charge to a substrate.
As shown in FIG. 2, the conventional back bias voltage level detector of FIG. 1 includes resistors R1 and R2 connected in series between a ground voltage V.sub.SS and a back bias voltage V.sub.BB, a pull-up resistor R3 and an NMOS pull-down transistor N connected in series between an external voltage V.sub.CC and the back bias voltage V.sub.BB, and inverters IN1 and IN2 connected to the pull-up resistor R3 and the pull-down transistor N.
A gate of the NMOS pull-down transistor N is connected between the resistors R1 and R2.
The operation of the back bias voltage level detector will now be explained with reference to the accompanying drawings.
First, the serial resistors R1 and R2 divide the back bias voltage V.sub.BB and bias the NMOS pull-down transistor N.
If the back bias voltage V.sub.BB is varied, a gate-source voltage V.sub.GS1 of the NMOS pull-down transistor N is varied.
Here, a current I.sub.R3 applied to the pull-up resistor R3 can be expressed as follows based on the voltage difference between the voltage V21 and the external voltage V.sub.CC between the pull-up resistor R3 and the NMOS pull-down transistor N. ##EQU1##
In accordance with the above expression, the current I.sub.R3 applied to the pull-up resistor R3 is varied with the external voltage V.sub.CC.
If the gate-source voltage V.sub.GS1 of the NMOS pull-down transistor N is decreased, the current I.sub.N applied to the pull-up resistor R3 is decreased. Subsequently, the current driving capacity of the NMOS pull-down transistor N is decreased, so that a node 21 becomes a high electric potential.
Here, since the oscillation enable signal OSCEN becomes the high electric potential, the back bias voltage oscillator 2, as shown in FIG. 1, outputs the pulse signal OSC.
When the pulse signal OSC is inputted to the back bias voltage pump 3, the absolute value of the back bias voltage V.sub.BB is increased because the negative electric charge is applied to the substrate by a pumping operation.
Therefore, the absolute value of the back bias voltage V.sub.BB is increased, and the gate-source voltage V.sub.GS1 of the NMOS pull-down transistor N is increased. As a result, the current I.sub.N reaches higher than the current I.sub.R3 applied to the pull-up resistor R3, so that the node 21 becomes a low electric potential.
Since the oscillation enable signal OSCEN is the low electric potential, the back bias voltage oscillator 2 does not output the pulse signal OSC and the back bias voltage pump 3 does not operate to pump.
FIG. 3 is illustrating another conventional back bias voltage level detector of the back bias voltage generator shown in FIG. 1. As shown in FIG. 3, another conventional back bias voltage level detector includes a PMOS pull-up transistor P substituting for the pull-up transistor R3 in the conventional back bias shown in FIG. 2. In the PMOS pull-up transistor P, a gate, source, and drain are connected to the ground voltage V.sub.SS, the external voltage V.sub.CC, and a drain of a NMOS pull-down transistor N, respectively.
The operation of the another conventional back bias voltage level detector will now be explained with reference to the accompanying drawings.
The resistors R1 and R2 connected in series divide the back bias voltage V.sub.BB and bias the NMOS pull-down transistor N. Here, if the back bias voltage V.sub.BB is varied, the gate-source voltage V.sub.GS1 of the NMOS pull-down transistor N is varied. The drain current I.sub.P of the PMOS pull-up transistor P can be expressed as follows. ##EQU2## where V.sub.GS2 denotes the gate-source voltage of the PMOS pull-up transistor P, and the value of V.sub.GS2 is the same as -V.sub.CC. V.sub.T and B denote a threshold voltage and a constant, respectively.
According to the expression above, the drain current I.sub.P of the PMOS pull-up transistor P is varied with the external voltage V.sub.CC.
When the gate-source voltage V.sub.GS1 of the NMOS pull-down transistor N is decreased, the current I.sub.N becomes smaller than the drain current I.sub.P of the PMOS pull-up transistor P. Accordingly, since the current driving capacity of the NMOS pull-down transistor N becomes small, node 31 becomes a high electric potential.
Here, the oscillation enable signal OSCEN becomes the high electric potential, and the back bias voltage oscillator 2, as shown in FIG. 1, outputs the pulse signal OSC.
Therefore, since the pulse signal OSC is inputted to the back bias voltage pump 3, and the negative electric charge is supplied to the substrate through a pumping operation, the absolute value of the back bias voltage V.sub.BB is increased.
When the absolute value of the back bias voltage V.sub.BB is increased, the gate-source voltage V.sub.GS1 of the NMOS pull-down transistor N is increased, and the current I.sub.N of the NMOS pull-down transistor N is increased. Thus, when the current I.sub.N of the NMOS pull-down transistor N is higher than the drain current I.sub.P of the PMOS pull-up transistor P, the node 31 becomes the low electric potential.
Therefore, the oscillation enable signal OSCEN becomes the low electric potential, and the back bias voltage oscillator 2 does not output the pulse signal OSC, and the back bias voltage pump 3 does not pump the negative electric charge to the substrate.
FIG. 4 is illustrating a relationship between the back bias voltage V.sub.BB and the threshold voltage V.sub.T.
As shown in FIG. 4, when the absolute value of the back bias voltage V.sub.BB is increased, namely, the back bias voltage V.sub.BB has a larger negative value, the threshold voltage V.sub.T of the NMOS pull-down transistor N is increased.
Here, the threshold voltage V.sub.T can be expressed as follows. ##EQU3## where V.sub.TO denotes the threshold voltage in an initial state, V.sub.sb denotes a voltage between the source and the substrate, and r denotes a constant varying with the doping of the substrate in the value a range of 0.4&lt;r&lt;1.2.
Thus, the larger the absolute value of the back bias voltage V.sub.BB, the larger the threshold voltage V.sub.T. In the conventional back bias voltage level detector, a large threshold voltage slows down the operational speed of the NMOS pull-down transistor N.
Thus, the conventional back bias voltage level detector does not appropriately latch the input. Moreover, since high electric field is applied to the junction of the NMOS pull-down transistor where the high voltage V.sub.BB is supplied, the reliability of the system is degraded.